Many circuits including integrated circuit devices require the charging of large capacitances for operation. One such integrated circuit device is a flash memory device; a nonvolatile memory which retains stored data when power is removed. A common type of flash memory architecture is the “NAND” architecture, so called for the resemblance which the basic memory cell configuration has to a basic NAND gate circuit.
A flash memory device can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory device comprises a memory array, which includes a large number of memory cells and peripheral support circuits. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
The operation of a flash memory requires charging and discharging the capacitances associated with the memory cells, bit lines, and other components within the device, which can be on the order of 50 nF. Charging these capacitances requires a large amount of current.
FIG. 1 illustrates a conventional circuit 10 for regulating current to charge the capacitance 104 within a NAND flash memory device. The capacitance 104 may be a capacitance associated with memory cells, bit lines and/or other components and lines within the flash memory device. An external power supply 100 supplies an external voltage Vext that is higher than the regulated voltage Vcc required for the general operation of the NAND flash memory device and other circuits 106 present on the same integrated circuit (IC) chip. An operating voltage regulator 102 converts the external voltage Vext to the lower operating voltage Vcc, which is then supplied to the components of the flash memory array and the other circuits 106.
The operating voltage Vcc is used to charge the capacitance 104. However, if the charging current I2 is uncontrolled, the capacitance 104 of the NAND flash memory may charge too quickly, causing the operating voltage Vcc to drop. This drop causes noise in the operating voltage Vcc, which adversely impacts the operation of the other circuits 106.
A technique for controlling the charging current I2 is to use a current mirror circuit 108 to maintain the charging current I2 equal to a reference current Iref. The current mirror circuit 108 includes two transistors 120 and 122 whose gates are connected to each other and to the reference current Iref.
The current mirror circuit 108 restricts the charging current I2 to the known amount of the reference current Iref and thus reduces potential noise from impacting the operating voltage Vcc. However, because the capacitance 104 of the flash memory is charged using less current, the amount of time needed to charge the capacitance 104 is increased. Therefore, the reduction of noise in the operating voltage Vcc is traded off for an increased time required to charge the capacitance 104.
A method and apparatus is therefore needed for charging a large capacitance of a circuit such as an integrated circuit device, e.g., a flash memory device, quickly without disrupting the operating voltage supplied to other circuits on the same integrated circuit chip.